1. Field of the Invention
The embodiments described herein relate generally to video processing circuits and methods, and more particularly to video frame synchronization using sub-frame memories.
2. Description of Related Art
Modern video processing circuits support an increasingly large array of input and output video timing formats. There are several problems presented for these processing circuits. First, pixel data rate conversion requires memory storage having a high bandwidth interface to contain pixel data written at an input rate and then read back at a different output rate. For example, the video timing formats range from the legacy standard-definition television video (SDTV) to the modern ultra-high definition television (UHDTV). The pixel sample and clock rate of video synchronization timing varies between these formats from the original 13.5 Mega Hertz (MHz) timing in SDTV applications to 350+ MHz in UHDTV applications. Modern video systems often handle the conversion of pixel and clock rates between formats that differ in pixel rate by up to 50 times from one format to another. Furthermore, a conversion from a pixel processing rate to a video standard rate, or from a video standard rate to a pixel processing rate may be required by a system.
Second, the capture of active data lines within an input format delivered over a specific time interval is converted to a display output format with active lines of data delivered over a different time interval. This conversion can involve an extensive use of memory storage and a significant increase in processing latency.
Third, filtering of video input timing aberrations, or “jitter,” in the received clock and input timing signals, requires further buffering to filter the jitter and achieve an averaged, constant output rate. The passing of jitter through a system from its input to its output is undesirable, can lead to standards timing non-compliance, and can result in the failure to operate downstream system components.
Traditional video synchronization systems utilize external dynamic RAM (DRAM) as a frame buffer memory. This frame buffer captures input video at an input rate and displays output video at a display rate and is used to resolve the three problems listed above. However, this external frame buffer is expensive, and may be limited by technical or cost driven capacity and bandwidth constraints.
What is needed is a frame buffer solution that achieves a reduction in storage requirements to resolve the above problems.